The present invention relates generally to a high voltage tolerant I/O circuit, and more particularly to an I/O circuit using a native NMOS transistor that improves the I/O circuit's performance.
As the semiconductor technology develops, an integrated circuit often contains some devices operating at a high voltage level and other devices operating at a low voltage level. The low voltage devices may not tolerate a high voltage signal. Device failures happen frequently, when the low voltage devices operate with the high voltage signal. In order to protect the low voltage devices from the high voltage signals, the integrated circuit often includes an I/O circuit as an interface between the low voltage devices and the high voltage devices. The I/O circuit allows the low voltage devices to communicate with the high voltage devices, while protecting the low voltage devices from the high voltage signals.
One conventional approach of designing the I/O circuit has been focused on the structure of individual devices in the I/O circuit. For example, the conventional approach has used a dual-oxide structure for low voltage devices interfacing with high voltage devices. The thickened oxide helps a low voltage device sustain a higher voltage. However, this approach has some problems. The dual-oxide structure complicates the manufacturing processes because its manufacturing process may not be compatible with those for manufacturing ordinary devices. This results in a longer development cycle time and additional costs.
Another conventional approach to the I/O circuit takes circuit designs into account. One type of the I/O circuit is a circuit interfacing between a high voltage circuit and a low voltage circuit. The I/O circuit is composed of low voltage devices that tolerate high voltage inputs, and output signals at a low voltage level. Such I/O circuit often operates in a three-state mode wherein the I/O circuit would be placed in one of the three states: 1) asserting a low voltage logic “1” to a pad connected to the high voltage circuit; 2) asserting a logic “0” to the pad; and 3) asserting neither “1” nor “0” to the pad so that the low voltage circuit and the high voltage circuit can operate at their own voltage levels without interference therebetween.
Switching devices are used to switch the I/O circuit among the three states. The switching devices are often a set of correlated PMOS and NMOS transistors. The performance of the I/O circuit greatly depends on the switching speed of those switching devices when the I/O circuit operates in the three state mode. The greater the switching speed, the better the performance of the I/O circuit. Conventionally, the switching speed of those switching devices are much less than satisfactory. For example, a PMOS transistor in a conventional I/O circuit requires 3.3 V to completely turn it off. Due to the I/O circuit's limits, the circuit initially charges the gate of the PMOS to a voltage level less than 3.3 V, such as 2.6 V. Then the voltage level of the gate would be slowly raised up to 3.3 V. The slow charging process results in a slow switching speed of the PMOS transistor. Many failures caused by the slow switching speed have been found when the I/O circuit operates at a clock speed higher than 100 MHz. This poses a bottleneck on the I/O circuit's performance.
What is needed is an I/O circuit that has a faster switching speed when it operates in a three state mode in order to improve its performance.